Why your Core 2 processor appear to not have CMPXCHG16B
From http://download.intel.com/design/processor/specupdt/318733.pdf :
"AW67. Enabling PECI via the PECI_CTL MSR Does Not Enable PECI and May Corrupt the CPUID Feature Flags
Problem: Writing PECI_CTL MSR (Platform Environment Control Interface Control Register) will not update the PECI_CTL MSR (5A0H), instead it will write to the VMM Feature Flag Mask MSR (CPUID_FEATURE_MASK1, 478H).
Implication: Due to this erratum, PECI (Platform Environment Control Interface) will not be enabled as expected by the software. In addition, due to this erratum, processor features reported in ECX following execution of leaf 1 of CPUID (EAX=1) may be masked. Software utilizing CPUID leaf 1 to verify processor capabilities may not work as intended.
Workaround: It is possible for the BIOS to contain a workaround for this erratum. Do not initialize PECI before processor update is loaded. Also, load processor update as soon as possible after RESET as documented in the RS – Wolfdale Processor Family Bios Writers Guide, Section 14.8.3 Bootstrap Processor Initialization Requirements. "
The CMPXCHG16B feature flag is one of the flags that is reported in ECX.
This erratum only affects E0/R0 steppings of 45nm Core 2, as you can see in the Summary Table of Changes.
Generally a BIOS update will contain the needed microcode update mentioned above.
For those who have Intel motherboards, from https://communities.vmware.com/message/1765787 :
"I got fed up and went to Intel on this one. One of their second level people finally gave me the suggestion that I should again flash the BIOS update, but use the method for full bios refresh, rather than the windows-based update process. I suspect that the microcode fix referred to in AV69 is in a part of the bios core that is not updated unless you do the full refresh."
"AW67. Enabling PECI via the PECI_CTL MSR Does Not Enable PECI and May Corrupt the CPUID Feature Flags
Problem: Writing PECI_CTL MSR (Platform Environment Control Interface Control Register) will not update the PECI_CTL MSR (5A0H), instead it will write to the VMM Feature Flag Mask MSR (CPUID_FEATURE_MASK1, 478H).
Implication: Due to this erratum, PECI (Platform Environment Control Interface) will not be enabled as expected by the software. In addition, due to this erratum, processor features reported in ECX following execution of leaf 1 of CPUID (EAX=1) may be masked. Software utilizing CPUID leaf 1 to verify processor capabilities may not work as intended.
Workaround: It is possible for the BIOS to contain a workaround for this erratum. Do not initialize PECI before processor update is loaded. Also, load processor update as soon as possible after RESET as documented in the RS – Wolfdale Processor Family Bios Writers Guide, Section 14.8.3 Bootstrap Processor Initialization Requirements. "
The CMPXCHG16B feature flag is one of the flags that is reported in ECX.
This erratum only affects E0/R0 steppings of 45nm Core 2, as you can see in the Summary Table of Changes.
Generally a BIOS update will contain the needed microcode update mentioned above.
For those who have Intel motherboards, from https://communities.vmware.com/message/1765787 :
"I got fed up and went to Intel on this one. One of their second level people finally gave me the suggestion that I should again flash the BIOS update, but use the method for full bios refresh, rather than the windows-based update process. I suspect that the microcode fix referred to in AV69 is in a part of the bios core that is not updated unless you do the full refresh."
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